A Robust Lock Aided Circuit for Sub-Sampling Phase-Locked Loop
Current research demonstrates that phase-locked loop(PLL)based on sub-sampling phase detector(SSPD)can achieve much lower in-band phase noise.However,in systems on chip(SOCs)application,PLLs are susceptible to interference from substrate or power supply coupling,which may cause the PLLs unlock and potentially unable to recover.To address this issue,this paper proposes a robust lock aided circuit for sub-sampling phase-locked loop(SSPLL)that combines a frequency-locked loop(FLL)and a digital lock detector(DLD).Simulation results indicate that the proposed circuit greatly improves PLL-robustness to substrate or power supply interference compared to traditional SSPLL while maintaining its low phase noise merit,which is of significance for SSPLL reliability in mass production and application.
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维普
