The circular electron positron collider(CEPC)experiment poses extremely demanding requirements on the spatial resolution of the vertex detector.The prototype chip of SOI pixel sensor CPV-4 employs 3D-SOI technology to meet the high spatial resolution needed for CEPC.This work primarily investigates the logic layer circuit design and verification under 3D-SOI technology for CPV-4.The logic layer,as the upper part of the CPV-4 3D chip,includes the storage and readout functions for particle hit information,utilizing a compact pixel logic design and an efficient priority encoding readout logic design.The test system implements logic interaction,data transmission,and user interface software and hardware functions based on the IPBUS protocol.Meanwhile we also developed an emulator module that mimics the logic layer's functionality and interface.Through comparative testing of the emulator module,the individual upper-tier chip,and the upper-tier logic layer after 3D integration,the upper-tier logic layer's circuit functionality is fully verified,demonstrating that 3D integration processes such as bonding pad,thinning,and top metallization do not adversely affect the on-chip logic layer.Preliminary progress has been made in the design of the logic circuit for the 3D-SOI pixel chip and the development of 3D integration technology.
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