Based on the MIPI D-PHY physical layer transmission protocol,a high-speed and low-power self-bi-ased comparator circuit is designed,and the circuit is theoretically analyzed and simulated.The overall struc-ture of comparator is composed of two stages of op-amps:the common gate,the common source and the NMOS transistor working in the linear region form the first-stage amplification structure,and the op-amp with the current source as the load forms the second-stage amplification structure.The differential signal is in-put through the NMOS source,which improves the common-mode voltage receiving range of the signal.There is no additional current source bias in the circuit structure,which improves the data transmission rate and reduces power consumption.The circuit is designed based on SMIC 0.18 μm CMOS process,powered by 1.8 V voltage.Simulation results show that the high-speed comparator can accurately receive differential sig-nals with low common-mode voltage,the DC gain is 37.4 dB,and the transmission rate reaches 2.5 Gb/s;the power consumption is 326 μW/(Gb/s);the common-mode voltage range of the received differential signal reaches 30-330 mV.
mobile industry processor interface(MIPI)high-speed receiving circuitMIPI D-PHY physical layerCMOS image sensorhigh-speed comparator
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