Stochastic architecture design for second-order edge detection algorithm
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数字图像边缘是具有明显亮度变化的像素集合,边缘检测是识别图像边缘的最佳方法.其中,二阶边缘检测算法具有很强的边缘定位能力,但在硬件实现上需要消耗大量资源,且易受到电路的内部噪声影响.文章提出拉普拉斯(Laplace)和高斯拉普拉斯(Laplacian of Gaussian,LoG)2 种常见二阶边缘检测算法的随机电路结构,并控制输入比特流的相关性来优化电路,进一步提高运行效率.实验结果表明,相比于传统的加权二进制实现,该电路消耗更少的功耗和电路面积,同时拥有更高的容错性.
An edge in a digital image is a collection of pixels with significant brightness variations,and edge detection is the best method to identify the edges of an image.Among them,the second-order edge detection algorithm has a strong edge localization capability,but it consumes a lot of resources in hardware implementation and is vulnerable to internal noise in the circuit.This paper proposes the stochastic circuit structure for two common second-order edge detection algorithms,Laplace and Laplacian of Gaussian(LoG),and controls the correlation of the input bitstream to optimize the circuit and further improve the operational efficiency.Experimental results show that the circuit structure consumes less power and circuit area while possessing higher fault tolerance than the conventional weighted binary implementation.
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