Based on the TSMC 0.18 μm CMOS technology,a charge pump phase-locked loop(CPPLL)suitable for fast locking in wide bandwidth is designed.An adaptive fast-lock structure is used to com-pare the frequency and phase of the reference signal with those of the feedback signal.By turning on the high current fast-lock and small current fast-lock paths,the capacitor in the loop filter is dis-charged so that the control voltage of the voltage controlled oscillator(VCO)drops near the lock lev-el,thereby minimizing the locking time.SPECTRE simulation verifies that at 1.8 V supply voltage and 768 MHz output frequency,the locking time only needs 1.5 μs,which reduces 78％,and the power consumption is 3.6 mW.
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