Design of energy-efficient low-latency BNN hardware accelerator
There are a large number of zero values used in the operation of binary neural network(BNN)applications,which leads to the surge of computations,as well as computing delay and com-puting power caused by repeated operations of the same weight data and feature graph data in BNN.In this paper,the methods of all-zero skipping and precomputed result caching are proposed.The pro-posed methods can effectively reduce the computation cost,computing delay and computing power.In addition,a BNN hardware accelerator based on field programmable gate array(FPGA)is designed and applied to handwritten digit recognition system.The experimental results show that after applying the proposed methods,the average power efficiency of the accelerator can reach 1.81 TOPs/W at the fre-quency of 100 MHz,which is 1.27-4.34 times higher than that of other BNN accelerators.
万方数据
维普
