一种高频锁相频率合成器的设计与实现
Design and Implementation of a High Frequency Phase-Locked Frequency Synthesizer
杨婧1
作者信息
- 1. 河北北芯半导体科技有限公司,石家庄 050051
- 折叠
摘要
为满足高频率信号基准的需求,设计了 5.5 GHz频率的锁相频率合成器.采用电荷泵锁相环(CPPLL)为核心器件,组合适配的压控振荡器(VCO),再搭配环路滤波器与反馈网络,并且使用MCU控制板与上位机软件进行参数配置,完成了目标频率的输出.实践证明方案可行有效,输出的信号频率不仅误差小,并且具有较好的杂散抑制,可为同类方案的设计和调试提供一定参考.
Abstract
In order to meet the requirement of high frequency signal benchmark,a phase-locked frequency synthesizer with 5.5 GHz frequency is designed.The charge pump phase-locked loop(CPPLL)is used as the core device,and the adaptive voltage-controlled oscillator(VCO)is combined.Then the loop filter and feedback network are combined,and the parameters are configured by MCU control board and host computer software to complete the output of target frequency.The practice proves that the scheme is feasible and effective.The output signal frequency not only has small error,but also has good spurious suppression,which can provide a certain reference for the design and debugging of similar schemes.
关键词
频率合成器/锁相环/压控振荡器/环路滤波Key words
frequency synthesizer/phase-locked loop/voltage-controlled oscillator/loop filter引用本文复制引用
出版年
2024
NETL
NSTL
万方数据