Design and Implementation of a High Frequency Phase-Locked Frequency Synthesizer
In order to meet the requirement of high frequency signal benchmark,a phase-locked frequency synthesizer with 5.5 GHz frequency is designed.The charge pump phase-locked loop(CPPLL)is used as the core device,and the adaptive voltage-controlled oscillator(VCO)is combined.Then the loop filter and feedback network are combined,and the parameters are configured by MCU control board and host computer software to complete the output of target frequency.The practice proves that the scheme is feasible and effective.The output signal frequency not only has small error,but also has good spurious suppression,which can provide a certain reference for the design and debugging of similar schemes.
frequency synthesizerphase-locked loopvoltage-controlled oscillatorloop filter
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