Multi-channel data aligner is a common digital circuit in the high-speed and real-time signal processing systems with field programmable gate array(FPGA)architecture.Due to the inconsistency of multi-channel high-speed data transmission paths,a synchronous alignment device needed to be designed at the receiving end.In this paper,a multi-channel high-speed data alignment device based on FPGA was designed by using hardware program-ming language,which had the characteristics of clear control logic,simple structure and strong scalability.The de-vice mainly included a FIFO clock domain conversion module,a FIFO read/write enabled control module,and a data alignment module in the master clock domain.
FPGAmulti-channel high speed data transmissionsynchronous alignment
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