科学技术创新2024,Issue(6) :91-94.

硅基芯片低空洞率底部填充工艺技术研究

Research on Low Porosity Underfill Process Technology of Silicon-based Chip

兰元飞 焦庆 姬峰 张鹏哲 孙浩洋 尤嘉 郭珍荣
科学技术创新2024,Issue(6) :91-94.

硅基芯片低空洞率底部填充工艺技术研究

Research on Low Porosity Underfill Process Technology of Silicon-based Chip

兰元飞 1焦庆 1姬峰 1张鹏哲 1孙浩洋 1尤嘉 1郭珍荣1
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作者信息

  • 1. 北京遥感设备研究所,北京
  • 折叠

摘要

以相控阵天线接收子阵硅基芯片为研究对象,从底部填充点胶针头选型、倒装芯片清洗、底部填充胶分配模式方面研究了硅基芯片底部填充工艺技术,测试了芯片底部填充外观、芯片底部填充空洞率以及接收子阵电性能.结果表明使用合适的点胶针头、选取适宜的清洗条件、采用适宜的底部填充胶分配模式完成底部填充的硅基芯片边缘胶层无开裂、无空洞,底部填充胶高度约为芯片厚度的2/3,底部填充区总空洞率<10%,单个空洞率<2%,底部填充后接收子阵增益下降≤2 dB,满足接收子阵性能指标要求.实现了接收子阵硅基芯片低空洞率底部填充工艺技术的应用.

Abstract

This paper takes the silicon-based chip of the receiving array for phased array antennas as the research object,the underfill technology of silicon-based chip is studied from the aspects of selection of dispensing needles、flip chip cleaning and underfill glue allocation mode,the appearance、void ratio of silicon-based chip and electrical performance of receiving array are tested,the results show that there are not cracking and hole in the adhesive layer edge of silicon-based chip which is underfilled by using appropriate dispensing nozzle、selecting appropriate cleaning conditions and using appropriate underfill glue allocation mode,the height of the underfill glue is about two-thirds of the the chip thickness,the total void rate of silicon-based chip is less than 10%,the single void rate of silicon-based chip is less than 2%,the gain decrease of the receiving array is less than or equal to 2 dB after underfilling,the performance requirements of the receiving array are meeted.The application of underfill technology with low void rate for silicon-based chip of the receiving array is achieved.

关键词

硅基芯片/底部填充/工艺技术

Key words

silicon-based chip/underfill/process technology

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出版年

2024
科学技术创新
黑龙江省科普事业中心

科学技术创新

影响因子:0.842
ISSN:1673-1328
参考文献量8
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