基于RISC-V的IOMMU设计
Design of IOMMU Based on RISC-V
王镇道 1班贵龙 1胡锦 1焦旭峰1
作者信息
- 1. 湖南大学 物理与微电子科学学院,湖南 长沙 410082
- 折叠
摘要
在半导体技术受到管控的背景下,实现芯片的完全自主可控已成为现今半导体技术发展的重点.由于RISC-V具有开源、应用广泛的特性,研究RISC-V架构对于我国微处理器的自主可控具有重要研究意义.在微处理器系统中,由于物理资源的有限性和直接访问存储可能潜在危害,DMA访问I/O设备时将会受到诸多限制,从而影响访问性能.目前主流的方法是通过将I/O事务虚拟化,可以很好地解决这一问题.本文首次提出了一种基于RISC-V的I/O虚拟化架构,极大地加速了I/O访问进程,仅花费几个时钟周期就可快速完成I/O设备对内存的DMA请求.本设计将来可以作为IP,集成到RISC-V架构的处理器中,加速I/O设备对内存的访问.
Abstract
In the realm of semiconductor technology control,achieving complete autonomous chip control has emerged as a focal point in today's semiconductor technology advancement.Given its features of open source and widespread adoption,the study of RISC-V architecture holds significant importance for enabling microprocessor autonomous controllability.Within microprocessor systems,limitations on physical resources and potential risks associated with direct storage access necessitate restrictions on DMA access to I/O devices,thereby impacting access performance.The prevailing approach involves virtualizing I/O transactions to effectively address this issue.This article firstly proposes a I/O virtualization architecture based on RISC-V,which greatly accelerates the I/O access process,this architectrue consums a few clock period to complete DMA requests from I/O devices to memory.This design will be integrated into RISC-V architecture CPU as an IP,accelerating the access of I/O devices to memory.
关键词
虚拟化/缓存/RISC-VKey words
virtualization/cache memory/RISC-V引用本文复制引用
基金项目
国家自然科学基金资助项目(Z202301432394)
出版年
2024
国家科技期刊平台
NSTL
万方数据