Design of a Low-Cost Triple-Node-Upsettolerant Latch
[Purposes]With the development of semiconductor technology,the shrinking feature size of in-tegrated circuits has made them more sensitive to soft errors,necessitating reinforcement of the storage units in integrated circuits.[Methods]Experiments and simulations were conducted using Hspice.Based on the PTM32nm CMOS process,a low-cost triple node upsets tolerant latch(LTNTL)structure was pro-posed.[Findings]The latch consists of 2 single-node self-recovery modules,1 secondary error intercep-tion module,and 3 transmission gates.Each self-recovery module consists of a Schmitt trigger and a clock-gating Schmitt trigger connected in a loop structure,effectively achieving tolerance to TNU.[Con-clusions]Simulation results demonstrate that compared to other latches with same functions,the pro-posed latch has complete TNU tolerance capability and reduces power consumption,delay,area,and power-delay product by approximately 37.58%,41.25%,27.77%,and 75.83%,respectively.
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