系统级封装中的键合线互连电路的优化设计
Design and Optimization of Bonding Wire Interconnect Circuits in System Level Packaging
沈仕奇1
作者信息
摘要
阐述键合线互连结构的建模,分析了键合线垂直间距和水平间距对寄生参数以及数字信号时序的影响.仿真结果对键合线垂直互连设计有实际指导作用.
Abstract
This paper expounds the modeling of bonding wire interconnection structures and analyzes the effects of vertical and horizontal spacing of bonding wires on parasitic parameters and digital signal timing.The simulation results have practical guidance for the design of vertical interconnection of bonding lines.
关键词
集成电路/系统级封装/键合线/寄生参数/信号完整性Key words
integrated circuits/system level packaging/bonding wires/parasitic parameters/signal integrity引用本文复制引用
出版年
2024
NETL
NSTL
维普
万方数据