This paper describes the characteristics of the RISC-V instruction set architecture and designs a processor core that supports a subset of RV64IM instructions.Firstly,it analyzes the impact of pipeline on processor performance and uses a five stage pipeline to improve processor throughput.Secondly,it optimizes processor performance using branch prediction modules and cache caching modules.Finally,it uses FPGA to validate the processor design,and at a 50MHz clock,the CoreMark runs at 2.86/MHz.
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