Study on methods to Improve Process Stability in the Photoresist Etching Back Process of the 28nm High-K Metal Gate Technology
This paper expounds that In the 28nm high-K metal gate technology,to address the issue of the stephigh between NMOS and PMOS regions,the main solution is to insert a photoresist etchback(PREB)loop before the metal gate manufacturing process.Through this process,it is possible to ensure consistent gate heights between NMOS and PMOS regions.However,the main difficulty of this scheme in production is that the second etch back(EB2)process is unstable.The etching rate and within wafer inline distribution will change significantly with the increase of process time,resulting in high variation of the measurement parameter"horn height"(the gap between the spacer1 silicon dioxide and the gate height),which is easy to cause defects and cannot be safely produced.In this paper,the reasons of the EB2 etching process instability in 28nm high-K metal gate technology are discussed in detail,and the feasible solutions are given for the anomalies in the actual production process,which is conductive to maintaining the stability of the chamber's microenvironment and improving the product quality.
integrated circuit manufacturing28nmhigh-K metal gatephotoresist etching backprocess stability
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