首页|基于PCM的长线高速传输收发模块设计

基于PCM的长线高速传输收发模块设计

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在飞行试验时为解决PCM信号在传输过程中随着通讯速度和距离增加出现丢数误码等传输可靠性问题,提出了一种基于PCM收发模块为一体的长线高速数据传输方案.设计以Xilinx的Kintex7系列FPGA为控制芯片利用差分线路驱动器DS26C31将PCM码差分输出驱动实现了逻辑电平的转换,通过光电耦合器FODM8071进行隔离式通信提高数据接收的高抗噪能力.为了进一步保证远距离高速数据接收的准确性和可靠性,还优化了PCM码接收单元的逻辑设计,并在数据发送时对链路状态标志位进行实时观测,增加传输异常时链路重连并重发的机制,解决了PCM数据回传时易丢失的问题.经大量试验测试,该电路工作稳定,抗干扰能力强,能实现30m双绞长线,最高速率达10 Mb/s的零误码稳定传输.
Design of Long-line High-speed Transmission Transceiver Module Based on PCM
In order to solve the transmission reliability problems of PCM signal with the increase of communication speed and distance,a long-line high-speed data transmission scheme based on PCM transceiver module is proposed in flight test.The design uses Kintex7 series FPGA of Xilinx as the control chip and differential line driver DS26C31 to drive the PCM code differential out-put to realize the logic level conversion,and uses the optocoupler FODM8071 for isolated communication to improve the high noise resistance of data receiving.In order to further ensure the accuracy and reliability of long-distance high-speed data receiving,the logic design of PCM code receiving unit is optimized,and the link status flag is observed in real time when the data is sent,and the link reconnection and retransmission mechanism is added when the transmission is abnormal,which solves the problem that PCM data is easy to lose when it is sent back.After a lot of tests,the circuit works stably and has strong anti-interference ability.It can re-alize the stable transmission of 30 m twisted-pair wire with the highest speed of 10 Mb/s.

FPGAPCMdecoding and receivingdifferential output drivehigh speed transmissionlink reconnection

赵文焘、焦新泉、杨志文、李辉景

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中北大学仪器科学与动态测试教育部重点实验室 太原 030051

FPGA PCM 解码接收 差分输出驱动 高速传输 链路重连

2024

舰船电子工程
中国船舶重工集团公司第709研究所 中国造船工程学会 电子技术学术委员会

舰船电子工程

CSTPCD
影响因子:0.243
ISSN:1627-9730
年,卷(期):2024.44(10)