An Adaptive and Low-Complexity Maximum Likelihood Sequence Detector for High-Speed PAM4 Wireline Transceivers
The high-speed serial transceiver is the key component for high-performance chips such as CPUs,NICs and switches.The decision feedback equalization(DFE)is the main equalization circuit of the high-speed serial transceiver.However,the high bit error rate(BER)of conventional DFE in high in-ter-symbol interference(ISI)channels limits the rate increase of serial transceiver.An adaptive reduced-state sequence detector(ARSSD)with low complexity is proposed in this paper.The detector adopts maximum likelihood sequence detection(MLSD)structure to reduce the detection BER,combines the Viterbi algo-rithm and the set-partitioning algorithm to reduce the complexity of operations and adopts zero-forcing(ZF)algorithm based ISI parameter acquisition to achieve the adaptive detector parameters.In this paper,the be-havioral simulation,circuit implementation and system verification of ARSSD are completed.The experi-mental results based on the analog front-end chip(AFEC)and the field programmable gate array(FPGA)show that:12～64Gbps PAM4 signals are faded by-8～-18dB@16GHz channel,the detection BER of 32×4 parallel ARSSDs is reduced by two orders of magnitude compared to the conventional DFE,which is con-sistent with the behavioral simulation results.
万方数据
维普
