VLSI Design and Implementation of Adaptive Deblocking Filter for HEVC
Deblocking filtering plays a crucial role in high efficiency video coding(HEVC)by effectively en-hancing the subjective quality of encoded images.It is one of the important means to improve overall video en-coding performance.To address the high complexity associated with deblocking filtering technology in HEVC hardware encoders,in order to save resource consumption,reduced processing cycles,and improved filtering ef-ficiency,a hardware algorithm and VLSI architecture for an adaptive deblocking filter in HEVC is proposed.First,based on the boundary rules of HEVC coding structure,a fast boundary judgment algorithm without recur-sive loop calculation is proposed to reduce the complexity of hardware implementation.Furthermore,based on the above boundary judgment results,a four-stage pipeline structure that can independently select the filter boundary for deblocking filtering is proposed to reduce the filter processing cycle.Finally,the luma and chroma components are filtered in parallel,utilizing a highly parallel and compatible shared memory architecture.This design not only enhances filtering efficiency but also minimizes memory resource consumption.Experimental results demonstrate that the hardware area of the designed deblock filtering structure is about 60％less than that of the existing structure under the TSMC90 nm process,and the maximum working frequency can reach 250 MHz,which can meet the real-time encoding of 8K@60fps ultra-high-definition video.
high efficiency video codingdeblocking filteringboundary judgmenthardware design
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