The erasure code fault-tolerant technology is widely used in current distributed storage systems.Compared with the multicopy fault-tolerant technology,the erasure code can not only significantly reduce the data storage costs,but can also provide improved data reliability and security.However,during the data storage process,the erasure code technology inevitably introduces additional computing overhead,increases the coding delay,and decreases the data write throughput.This study proposes an acceleration scheme of erasure code encoding based on the Field Programmable Gate Array(FPGA)to decrease the coding delay and increase the data write throughput.The specific work includes the following aspects.First,the advantages of high-speed parallel computing of the FPGA is used to speed up the erasure code algorithm and achieve parallel processing and timing optimization.Next,the off-chip DDR3 interface is expanded on the FPGA for data cache,which improves the reliability of communication,to solve the problem of data overflow in memory caused by the inconsistency of the transmission rate and processing rate between the upper computer and FPGA.In addition,the random access feature of DDR3 is used to fragment the data blocks.Finally,a hardware acceleration architecture based on the FPGA for the erasure code is designed for experimental verification.The experimental results show that the FPGA-based acceleration scheme improves the data write throughput by 2.7-93.0 times compared with the current mainstream open-source erasure code library Jerasure 2.0,particularly for the encoding and writing performance of smaller files.
国家科技期刊平台
NSTL
维普
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