Study of FPGA-based Error-controllable Floating-point Operation Accelerators
Floating-point operations are fundamental operations in the field of High-Performance Computing(HPC).In the context of big data and cloud computing,the amount of data that HPC platforms need to process is continuously growing,and the round-off error of floating-point arithmetic numbers will accumulate in large-scale,long-term operations.Therefore,it is crucial to ensure the reliability of the calculation results while improving the performance of floating-point operations.In response to these issues,based on the programmable,low-power,and flexible characteristics of a Field Programmable Gate Array(FPGA),a floating-point polynomial accelerator is designed mainly for complex single item operations.Based on the idea of error free transformation,the round-off error value is calculated and compensated to the floating-point value,such that the error can be controlled.Asynchronous and parallel methods are adopted to accelerate computation,and a CPU-FPGA platform is constructed to maximize the utilization of computing resources and ensure the efficiency of computing task execution.The data test results demonstrate that the accelerator can achieve a peak performance of 91.85 MFLOPs at the main frequency of 200 MHz in the numerical relativity simulation without limiting the symmetry.Compared to the performance of Intel i7 6700K CPU running the maximum number of threads,this accelerator achieved an acceleration ratio of 50.54,and achieved an average accurate result percentage of 53.6％and lower relative error under these conditions,demonstrating high reliability.
Field Programmable Gate Array(FPGA)floating-point operation acceleratorcontrollable errorheterogeneous systemhigh reliability
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