Research and Design of Five-Stage Pipelined RISC-V Microprocessor
To meet the requirements of low-overhead and high-performance applications in the embedded field,a 32 bit microprocessor based on the RISC-V open-source instruction set architecture has been developed.The processor adopts a five-stage pipeline structure of sequential launch,sequential execution,and out-of-order write back and realizes a combination of integer and multiply-divide instruction set modules.To cope with pipeline conflicts,the processor adopts a dynamic branch-prediction technique and designs data-correlation control and write back disorder mechanisms.The processor is designed using Verilog and builds a System on Chip(SoC)using an Advanced High-performance Bus(AHB)and an Advanced Peripheral Bus(APB)as interconnecting bus protocols.The processor logic functions are verified by writing RV32IM assembly instruction test programs in a simulation environment.Add timing constraints and physical constraints under the Vivado synthesis tool to perform logical synthesis on the processor code and analyze the utilization of processor hardware resources,and the synthesized code stream file is downloaded to the Xilinx Artix-7(XC7A200T-2FBG484I)Field Programmable Gate Array(FPGA)development board and runs at a main frequency of 50 MHz.In the CoreMark program at 50 MHz,the CoreMark running points reaches 3.25 CoreMark/MHz.The validation results show that the processor performance running points is the same as that of the ARM Cortex-M3 series processors,and under the premise of the same technical comparison indexes,the processor running points is better than that of the RISC-V processor comparison item.The designed processor logic function is correct and uses a low hardware overhead to achieve relatively high-performance indicators suitable for cost-constrained high-performance embedded applications.
万方数据
维普
