Design of PCIe Verification Platform in SoC Environment Based on UVM
The System of Chip(SoC)integrates multiple peripheral interfaces,the verification of which has become one of the most time-consuming steps in chip development.The PCIe protocol provides high-speed peer-to-peer serial interconnection services within the system,while supporting hot swapping,which has gradually become a universal bus protocol.When using conventional Hardware Description Languages(HDL)to validate PCIe interface designs,problems usually arise,such as difficulty in covering multiple design scenarios and boundary conditions in a short period,leading to insufficient verification.To address the above issues,this study utilizes Universal Verification Methodology(UVM)to build a PCIe interface validation platform.This platform adopts a UVM-defined framework and test classes,achieving top-level environmental integration and design of test constraints,with strong reusability and comprehensive verification.This implementation includes SoC system-level environmental integration,design,and connection of the modules to be tested,implementation of sequencer and monitor classes in the verification platform,and partial interface design.To ensure that the test cases cover as many design states and paths as possible,different functional points are divided deliberately,and constraint conditions are designed to evaluate the effectiveness and coverage of test cases using various coverage indicators.The experimental results show that the verification platform can curtail the verification cycle and increase the comprehensive coverage by more than 30％.
PCIe protocolverification platformUniversal Verification Methodology(UVM)coverage rateverification IP
万方数据
维普
