Research on wafer-scale chip mapping task based on genetic algorithm
In recent years,with the development of artificial intelligence,deep learning has become one of the most important computing loads today.The next generation of artificial intelligence(AI)and high-performance computing applications have put unprecedented demands on the computing power and communication capabilities of computing platforms.Wafer-scale chips integrate ultra-high-density tran-sistors and interconnect communication capabilities on the entire wafer,so it is expected to provide revo-lutionary computing power solutions for future AI and super-computing platforms.Among them,the huge computing resources and unique new architecture of wafer-scale chips pose unprecedented challen-ges to task mapping algorithms.Related research has become a major focus of academic research in re-cent years.This paper focuses on studying the mapping methods of AI tasks on wafer-scale hardware re-sources.By expressing the AI algorithm as multiple convolutional kernels and considering the computa-tional power characteristics of convolutional kernels,a mapping algorithm for wafer-scale chips is de-signed based on genetic algorithms.The simulation results under a series of mapping tasks verifies the effectiveness of the mapping algorithm and revealed the impact of parameters such as execution time and adapter cost on the cost function.
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