Design and FPGA implementation of a high-precision double step branching hybrid CORDIC algorithm
The CORDIC(coordinate rotation digital computer)algorithm is an approach used for computing trigonometric functions and other mathematical operations.It is widely applied in complex fields such as digital signal processing and computer graphics.The CORDIC algorithm,which only re-quires addition,subtraction,and shift operations,is particularly suited for hardware implementation.A limitation of the traditional CORDIC algorithm is its excessive number of iterations.Many studies have aimed to optimize this,but these optimizations often increase hardware overhead and may lead to preci-sion loss.To address this,this paper proposes an optimized CORDIC algorithm based on the Hybrid CORDIC algorithm and the double step branching CORDIC algorithm,called high-precision double step branching hybrid CORDIC(HD CORDIC)algorithm.This algorithm reduces the number of iterations to N/4+"1"(where N is the number of micro-rotation angles and the bit width),presents a new parti-tioning formula for the hybrid radix set to achieve high precision of ε＜2-(N-2),which is similar to the basic CORDIC algorithm(ε＜2-(N-1)),and does not require the calculation of the scaling factor K.The HD CORDIC algorithm employs a pipelined architecture with only N/4+3 pipeline stages(while the basic CORDIC algorithm without scaling factor compensation operation is N+2).This algorithm was implemented in hardware using Verilog and synthesized on the XILINX Zynq-7000 xc7z100ffv900-2 FPGA platform.Experimental results show that when the input angle bit width is 16,the operating fre-quency is 315.66 MHz and it only takes 6 clock cycles to complete one sine & cosine function operation.Compared with the XILINX CORDIC IP,the HD CORDIC algorithm reduces the processing time by 59.13％,the LUT overhead by 55.74％,the register overhead by 80.24％,and the power consumption by 35.99％.
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