多核堆栈处理器研究与设计
Research and design of multi-core stack processor
刘自昂 1周永录 2代红兵 2刘宏杰2
作者信息
- 1. 云南大学信息学院,云南昆明 650500
- 2. 云南大学信息学院,云南昆明 650500;云南大学 云南省高校数字媒体技术重点实验室,云南 昆明 650223
- 折叠
摘要
为满足日趋复杂的嵌入式环境对堆栈处理器和Forth技术的应用需求,在单核堆栈处理器模型研究的基础上,设计一种多核堆栈处理器模型.基于J1单核堆栈处理器模型,针对多核目标,增加计时器、中断等功能,形成新的L32单核堆栈处理器模型,并以该单核模型为内核,引入共享总线和十字开关互联方式的Wishbone总线、多端口存储器和面向多任务Forth系统的指令集,建立一种多核堆栈处理器模型L32-MC.利用该多核模型,在FPGA上实现4核和8核的L32-MC原型多核堆栈处理器.实验结果表明,4核和8核的L32-MC原型堆栈处理器满足高性能低功耗的多核处理器设计目标.
Abstract
To meet the application requirements of increasingly complex embedded environments for stack processors and Forth technologies,a multi-core stack processor model was designed based on the research of single-core stack processor model.Based on the J1 single-core stack processor model,a L32 single-core stack processor model was formed by adding timers and interrupts for multi-core target,which was taken as the core,and a multi-core stack processor model L32-MC was established by intro-ducing Wishbone bus with shared bus and cross-switch interconnection method.Using this multi-core model,the 4-core and 8-core L32-MC prototype multi-core stack processors were implemented on the FPGA.Experimental results show that the 4-core and 8-core L32-MC prototype stack processors reach the goals of high-performance and low-power multicore processor design.
关键词
多核堆栈处理器/Forth技术/Wishbone片上总线/多端口存储器/指令集/现场可编程门阵列/嵌入式Key words
multi-core stack processor/Forth technology/Wishbone bus/multi-port memory/instruction set/FPGA/embed-ded引用本文复制引用
出版年
2024
NETL
NSTL
万方数据