Design and Implementation of Specialized Instruction Accelerator for Hash Cryptography Algo-rithms
The rapid development of the Internet of Things has increasingly high requirements for the system performance and data security of embedded devices.Traditional general-purpose embedded processors have low efficiency in imple-menting cryptographic algorithms and cannot meet performance requirements well.In addition,embedded devices are also in low power consumption scenarios.To address the above issues,a low-power specialized instruction accelerator for hash cipher algorithms is designed on the Xilinx ZYNQ ZC706 embedded development platform.The accelerator includes a fetch decoding unit,an execution unit,and data access units,which achieves computation acceleration through multitasking data parallelism and specialized instructions.And a token mechanism is designed to solve the problem of data conflicts during instruction execution.On the basis of high-level synthesis(HLS)tools,the paper uses storage opti-mization to improve the access mechanism and effectively improve bandwidth utilization.The experimental results show that the working frequency of the accelerator is 100 MHz,and the ARM+FPGA scheme can achieve more than three times the acceleration effect compared to the single ARM scheme.The operating power consumption is only 2.23 W,and the accelerator can also be customized and expanded,with good flexibility.
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维普
