FastRMT:一种面向微体系结构创新的高速数据平面可编程系统

扫码查看

原文链接

万方数据
维普

中文摘要：网络数据平面可编程(Data Plane Programmability)给网络转发设备的数据平面赋予强大的可编程性,在不更换设备的情况下,可以动态部署新型机制与服务,例如路由转发核心机制、网络安全控制功能、网内计算加速服务等.由此,数据平面可编程成为业界和学术界高度关注的新兴技术,并已在主流云服务提供商投入应用.可重构匹配表架构(Reconfigurable Match Table Architecture,RMT)由于出色的处理性能和采用P4语言灵活编程的特性,成为数据平面可编程的热点研究方向.然而,受困于RMT架构复杂的体系结构设计、芯片闭源的服务机制以及门槛较高的FPGA设计开发,使得RMT研究人员难以通过FPGA,对RMT创新设计以及100 Gbps以上真实性能场景进行敏捷验证.本文提出并实现了一种数据平面可编程系统FastRMT,首次开源了FPGA级的系统实现.FastRMT支持RMT架构可编程协议解析、自定义规则匹配、超长指令字的并发动作执行引擎等核心功能,支持P4语言对系统进行编程.FastRMT具备松耦合与模块化的特点,研究人员可以替换模块或者对系统进行动态重构,从而实现新型机制或体系结构的敏捷开发与验证.本工作包含交换机原型与网卡原型两种版本,支持主流FPGA芯片,系统可完成100 Gbps的报文线速处理能力,1500 B报文处理延迟仅为1.22 μs,体现了FastRMT作为基础框架对微体系结构创新和生产线级别验证的优势和可行性.

外文标题：FastRMT:A High-Speed Data Plane Programmable System for Micro-Architecture Innovation

外文摘要：Network data plane programmability(Data Plane Programmability)gives powerful programmability to the data plane of network forwarding devices,allowing the deployment of new network protocols,updating security functions,and providing in-network computing acceleration services without updating devices.Due to these advantages,data plane programmability has become an emerging technology that is highly concerned by the industry and academia,and has been put into use by mainstream cloud service providers.Among them,Reconfigurable Match Table architecture(RMT)has become a hot research direction in the programmable data plane due to its excellent processing performance and flexible programming capability with P4 language.However,due to the complex design of the RMT architecture,the closed-source service mechanism of the chip,and the high development threshold of FPGA,it is currently difficult for researchers to innovatively design the micro-architecture of the RMT architecture through FPGA and perform in real performance scenarios(above 100 Gbps).Motivated by the need of research on data plane programmable micro-architecture,this paper proposes an open-source design of a flexible and high-speed programmable data plane prototype system for the first time.The system supports core functions such as RMT architecture programmable protocol parsing,custom rule matching,and action engines based on very-long instruction words,and supports programming of the system via P4 language.In addition,FastRMT also has the characteristics of loose coupling and modularity,which facilitates researchers to replace or reconstruct modules,thereby enabling agile development and verification of new mechanisms or architectures.This work includes two versions of switch prototype and network interface card prototype,supporting mainstream FPGA chips.The system can complete 100 Gbps line-speed packet processing capability,and the 1500 B packet processing delay is only 1.22 μs,which reflects the micro-architecture innovation of FastRMT as a basic framework.and the advantages and feasibility of production line-level verification.

外文关键词：

data plane programmabilityReconfigurable Match Table(RMT)micro-architecture,FPGA PrototypeProgramming Protocol-Independent Packet Processers(P4)

作者：

杨翔瑞、曾令斌、刘忠沛、陈颖文、吕高锋、杨程、苏金树

展开 >

作者单位：

国防科技大学计算机学院长沙 410072

湖南先进技术研究院长沙 410006

关键词：

数据平面可编程可重构匹配表微体系结构 FPGA原型可编程协议无关报文处理

基金：

国家自然科学基金国家自然科学基金湖南省自然科学基金国防科大青年自主创新科学基金

项目编号：

62372462U22B20052023JJ40682KQ2209027

出版年：

2024

DOI：

10.11897/SP.J.1016.2024.00473

计算机学报

中国计算机学会中国科学院计算技术研究所

计算机学报

CSTPCD北大核心

影响因子：3.18

ISSN：0254-4164

年,卷(期)：2024.47(2)

参考文献量46