Efficient Accelerator for Depthwise Separable Convolutional Neural Networks Based on RISC-V
In the era of artificial intelligence,RISC-V,as an emerging open-source Reduced Instruction Set Computing architecture,has become a new platform capable of adapting to evolving deep learning models and algorithms due to its advantages such as low power consumption,modularity,openness,and flexibility.However,in environments with constrained hardware resources and power,the basic RISC-V processor architecture falls short of meeting the high-performance computing demands of convolutional neural networks.To address this issue,this paper introduces a lightweight depthwise separable convolutional neural network accelerator based on RISC-V,aiming to compensate for the insufficient convolutional computation capabili-ties of RISC-V processors.The accelerator supports two key operators in depthwise separable convolution:depthwise convolution and pointwise convolution,and enhances resource utilization efficiency through shared hardware structures.The depthwise convolution computation pipeline employs an efficient Winograd convolution algorithm and reduces data redundancy by combining 2×2 data blocks into 4×4 data tiles.Additionally,by extending RISC-V instructions,the accelerator achieves more flexible configuration and invocation.Experimental results demonstrate significant acceleration in pointwise and depthwise convolution computations compared to the basic RISC-V processor,with a speedup of 104.40x for pointwise convolution and 123.63x for depthwise convolution.Meanwhile,the performance-to-power ratio of the accelerator reaches 8.7 GOPS/W.The combination of the RISC-V processor and the accelerator presented in this paper offers an efficient and viable choice for deploying convolutional neural networks in resource-constrained environments.
neural networksdepthwise separable convolutionReduced Instruction Set Computer-VWinograd fast convolutionhardware acceleration
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