随着片上系统(System on Chip,SoC)芯片规模与功能复杂度的膨胀,硬件加速器已成为大规模SoC的重要组成部分.为了缩短产品交付时间,有必要开发硬件加速器仿真模型,以在SoC设计初期支撑架构的探索与评估.在对硬件加速器的特点与建模需求进行分析的基础上,提出一种基于AXI验证IP(Verification IP,VIP)、SystemVerilog信箱和旗语的硬件加速器建模方法.该方法支持完备的总线协议特性,同时支持多个处理引擎的并行处理与乱序输出.以实际SoC项目中的通信基带加速器为例,对提出的建模方法进行介绍,并进行相应的系统级仿真与分析.所提出的建模方法可实现对硬件加速器总线行为的高效建模,能够有力支撑SoC验证以及系统架构评估,缩短项目的开发周期.
Design of Hardware Accelerator Simulation Model Based on VIP and SystemVerilog
With the expansion of the scale and functional complexity of System on Chip(SoC),hardware accelerator has become an important component of large scale SoC.In order to shorten product delivery time,it is necessary to develop a simulation model of hardware accelerator to support the exploration and evaluation of the architecture in the initial stages of SoC design.On the basis of analyzing the features and modeling requirements of hardware accelerators,a hardware accelerator modeling method based on AXI Verification IP(VIP)and SystemVerilog mailbox and semaphore is proposed.The method supports complete bus protocol features,as well as paralleled processing and disordered output with multiple processing engines.Taking the communication baseband accelerator in the actual SoC project as an example,the proposed modeling method is introduced,and corresponding system level simulation and analysis are conducted.The proposed modeling method can achieve efficient modeling of hardware accelerator bus behavior,effectively support SoC verification and system architecture evaluation,and shorten the development cycle of the project.