Design of Simulation Model of SoC Peripheral Components Based on UVM and AXI VIP
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维普
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随着片上系统(System on Chip,SoC)复杂度和集成度的提高,其对验证效率的要求也不断提高.传统的瀑布形式的系统设计流程中,各个开发子过程顺序执行.为了将功能模块开发与系统架构验证并行开展以缩短项目的交付时间,提出 了一种利用通用验证方法学(Universal Verification Methodology,UVM)验证 IP(Verification IP,VIP)进行 SoC外设组件快速建模的方法.使用事务级建模(Transaction-Level Modeling,TLM)模型模拟硬件行为代替未开发完成的功能模块产生数据流,使得在设计早期系统架构搭建完成后能更早地开展系统级测试,帮助评估总线架构性能和功能,提高验证效率.以网络处理器芯片中的数据转发模块为例,对SoC外设组件的建模方法进行了介绍,在系统级测试中进行了仿真验证.
With the increase of System on Chip(SoC)complexity and integration,there exists an increasing demand for verification efficiency.As for the traditional waterfall development method of system design,each subprocess of project development is sequential.In order to shorten the delivery time,functional module development and system architecture verification should be carried out in parallel.A quick modeling method for SoC peripheral components is proposed by using Universal Verification Methodology(UVM)Verification IP(VIP).Transaction-Level Modeling(TLM)model is used to simulate the hardware behavior,replacing undeveloped functional modules to generate the data flow,so that the system-level test can be carried out as soon as the system architecture of the early design is built,evaluating bus architecture performance and functionality and improving the efficiency of verification.Taking the data forwarding module of the network processor chip as an example,the modeling method is introduced and the TLM model is verified in the system-level test.
维普
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