RECONFIGURABLE IMPLEMENTATION OF HEVC DATA FLOW GRAPH BASED ON ARRAY PROCESSOR
This paper presents a reconfigurable implementation method of HEVC algorithm data flow graph based on array processor.Based on the dynamic reconstruction mechanism,the flexible switching between different partition methods and algorithms was completed.The data flow graph of typical coding algorithms in HEVC was redivided by depth first greedy parallel mode of time-domain pipelining of sub tasks after data flow graph partition.After that,a reasonable mapping scheme was designed.The intra prediction algorithm was verified on array processor based on Sobel operator value.The experimental results show that compared with the inter block pipelining scheme,the speedup ratio can reach 14.97,and the resource utilization and computing speed of each algorithm are improved.Compared with the fast intra prediction mode selection algorithm,each clock cycle can process 7.1 more pixels.
Data flow graphHEVCDepth first greedy searchReconfigurable array processor
万方数据
维普
