Design and implementation of UDP protocol stack IP core based on domestic FPGA
In order to solve the instability problem of foreign chip supply and meet the requirements of self-reliant and controllable design,the Ethernet-based UDP communication protocol is implemented in hardware mode on domestic FPGA,and SystemVerilog language is used to design a UDP protocol stack IP core.The IP core supports active ARP request,passive ARP response,ARP table query,ICMP protocol,IP protocol,UDP protocol,and inter-protocol arbitration control,and at the same time,it also supports AMD's triple-speed Ethernet IP core,able to be directly adapted to the triple-speed Ethernet IP core.The protocol stack IP core only adopts the common-ly used FIFO IP,and the rest are designed in the form of source code,which is easy to be transplanted and de-ployed on other domestic FPGAs.Finally,the designed IP core is tested on on SSMEC SMQ7K325TFFG900 chip.The test results show that the IP core can realize UDP protocol communication,with good performance.
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