The field-programmable gate array(FPGA)is also known as the FPGA chip,and it plays a crucial role in fields such as communications,security and industry.As the scale of FPGA chips continues to expand and their performance continues to improve,their number of modules,size of circuit netlists and connection complexity also increase.In this trend,how to effectively improve the verification efficiency and completeness of large-scale FPGA circuits has become more important.A complete,targeted and structured verification process method can compre-hensively check the coverage of circuit design and ensure the correctness of the function of FPGA chips.This paper detailedly describes the verification method of FPGA chips from the bottom layer to the top layer(module-level,subsystem-level,full chip-level),including details such as their respective verification methods,processes and em-phases,and explores how this method helps FPGA verification work.
FPGA chipValidation efficiencyValidation process methodFull chip-level validation
NETL
NSTL
万方数据
