Abstract
Developing low-power FETs holds significant importance in advancing logic circuits,especially as the fea-ture size of MOSFETs approaches sub-10 nanometers.However,this has been restricted by the thermio-nic limitation of SS,which is limited to 60 mV per decade at room temperature.Herein,we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize sub-thermionic SS in MOSFETs.Through high-throughput calculations,we established a guiding principle that combines the atomic structure and orbital interaction to identify their sub-thermionic transport poten-tial.This guides us to screen 192 candidates from the 2D material database comprising 1608 systems.Additionally,the physical relationship between the sub-thermionic transport performances and elec-tronic structures is further revealed,which enables us to predict 15 systems with promising device per-formances for low-power applications with supply voltage below 0.5 V.This work opens a new way for the low-power electronics based on 2D materials and would inspire extensive interests in the experimen-tal exploration of intrinsic steep-slope MOSFETs.
基金项目
Postgraduate Research & Practice Innovation Program of Jiangsu Province(KYCX22_0428)
国家自然科学基金重大研究计划培育项目(91964103)
江苏省自然科学基金(BK20180071)
中央高校基本科研业务费专项(30919011109)
江苏省"青蓝工程"项目()
江苏省"六大人才高峰"高层次人才项目(XCL-035)
Research Grant Council of Hong Kong(CRS_PolyU502/22)