Binary tree-based synthesis algorithm for Verilog case statement
Verilog case statements are conditional statements in the hardware description language.They are widely used in fields such as processors,network switches,and digital signal processing.They can optimize resource distribution in terms of efficiency through the use of multiplexers.However,the existing synthesis tool ABC which is based on the And-Inverter Graph logic representation cannot effectively synthesize such circuits.Therefore,in this paper we propose a novel logic representation named MUX-And-Inverter Graph(MAIG),and present a binary tree-based synthesis algorithm specifically for explicit circuits within Verilog case statements.In order to improve the efficiency of the algorithm and the quality of synthesis,the first step is to extract circuit feature parameters and perform matrix column transformation.The proposed process as a result reduces the number of MUX gates and levels.Next,depending on the 0 and 1 values of the matrix,a binary tree optimization algorithm is applied to partition the matrix which is implemented to recursively generate MAIG with a smaller area and smaller delay.Compared to ABC,the proposed algorithm achieves an average optimization by 72％in the number of logic gates and 52％in logic depth before technology mapping came into being.It also achieves an average improvement by 67％in circuit area and 33％in delay reduction after technology mapping became available.
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维普
