This paper presents a 9-bit differential successive approximation(SAR)analog-to-digital converter(ADC)based on 40 nm CMOS technology.The influences of the capacitor mismatch error and the parasitic effect are calculated through theoretical deduction,and simulated by a fast MATLAB Monte Carlo simulation model.The model can implement multi-structure performance comparison algorithms according to the constraints of various key parameters of the ADC.Based on the layout extraction,the actual parameters are brought back to the simulation model for rapid verification,which greatly reduces the iteration cost caused by architecture adjustment.The silicon chip area of the proposed ADC is only 0.0043 mm2,and the power consumption measured at a sampling rate of 125 kS/s is only 360 nW.For a 1.8 Vpp input signal of 2.6 kHz,an effective number of bits(ENoB)of 8.4 bit and 68.8 dB of spurious-free dynamic range(SFDR)are achieved.
analog-to-digital converter(ADC)successive approximation register(SAR)ultra-low powerbiosensing system
万方数据
维普
