RISC-V架构浮点运算单元的研究设计与UVM验证
Research,Design and UVM Verification of RISC-V Architecture Floating Point Operation Unit
梁光胜 1梁兆楷 1李朝洋 1杨松1
作者信息
- 1. 华北电力大学电气与电子工程学院,北京 102206
- 折叠
摘要
分析了基于RISC-V架构的浮点运算单元设计方法和运行流程.以System Verilog为验证语言,以VCS和Verdi为编译仿真软件,设计了多个底层UVM验证组件,搭建了浮点运算单元的UVM验证平台.针对功能验证点编写测试用例,根据基础情况和边界情况的多种浮点运算场景配置测试参数,进行了浮点运算单元的功能验证,分析了验证平台运行数据报告、运算结果的Verdi波形、代码覆盖率和功能覆盖率.
Abstract
The design method and operating process of the floating point operation unit based on the RISC-V architecture were analyzed.System Verilog was used as the verification language,and VCS and Verdi were used as the compiling simulation software,the multiple underlying UVM validation components were designed,the UVM verification platform of the floating point operation unit was built.The test cases for functional verification points were programmed,the test parameters were configured according to various floating point operation scenarios of basic and boundary conditions,and functional verification of floating point operation unit was carried out.The verification platform running data report,Verdi waveform of oper-ation results,code coverage and functional coverage were analyzed.
关键词
RISC-V/浮点运算单元/UVM验证/VCS/VerdiKey words
RISC-V/floating point operation unit/UVM verification/VCS/Verdi引用本文复制引用
出版年
2024
NETL
NSTL
万方数据