Research,Design and UVM Verification of RISC-V Architecture Floating Point Operation Unit
The design method and operating process of the floating point operation unit based on the RISC-V architecture were analyzed.System Verilog was used as the verification language,and VCS and Verdi were used as the compiling simulation software,the multiple underlying UVM validation components were designed,the UVM verification platform of the floating point operation unit was built.The test cases for functional verification points were programmed,the test parameters were configured according to various floating point operation scenarios of basic and boundary conditions,and functional verification of floating point operation unit was carried out.The verification platform running data report,Verdi waveform of oper-ation results,code coverage and functional coverage were analyzed.
RISC-Vfloating point operation unitUVM verificationVCSVerdi
NETL
NSTL
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