面向车载功能安全的低开销超标量双核锁步处理器架构设计
Design of a Low-Overhead Superscalar Dual-Core Lockstep Processor Architecture for Automotive Functional Safety
张承译 1王明羽 1虞志益 1李兆麟2
作者信息
- 1. 中山大学 微电子科学与技术学院,广州 510275
- 2. 清华大学 计算机科学与技术系,北京 100084
- 折叠
摘要
在车载功能安全领域,双核锁步架构是一种被广泛应用于解决处理器故障的冗余架构.为支持细粒度故障处理的超标量处理器提出一种新颖的双核锁步架构,通过以分支跳转指令的形式执行程序回滚,该架构能在故障发生的同一时钟周期内检测和纠正故障,且不需要额外的专用硬件模块来满足细粒度回滚的需求.还提出一种虚拟写回机制,该机制将特定数据传送到只读寄存器以防止故障衍生,使处理器无需在程序执行期间持续保存现场,从而显著节省了面积开销.试验结果表明,该架构对注入处理器的故障实现了较彻底的故障覆盖,对处理器原型的性能影响很小,与先前双核锁步相关的工作相比,时间和面积开销更小.
Abstract
In the field of automotive functional safety,the dual-core lockstep(DCLS)architecture is a redundancy architecture widely used for addressing processor faults.This paper proposes a novel dual-core lockstep architecture for superscalar processors that supports fine-grained fault handling.By executing program rollback in the form of a branch instruction,the proposed architecture can detect and correct faults within the same clock cycle they occur,without the need for additional hardware support.Furthermore,the virtual writeback(VW)mechanism is also presented,which feeds specific data to read-only registers to prevent fault propagation.This allows the processor to avoid continuous context saving during program execution,which reduces area overhead significantly.The experimental results show that this architecture achieves more thorough fault coverage with minimal impact on the processor performance,while exhibiting reduced latency and area overhead compared with the DCLS-related previous work.
关键词
双核锁步/处理器/故障处理/程序回滚Key words
dual-core lockstep/processor/fault handling/rollback引用本文复制引用
基金项目
国家重点研发计划(2020YFB1600202)
广东省重点领域研发计划(2021B0101410004)
广东省自然科学基金(2022A1515011708)
出版年
2024
国家科技期刊平台
NSTL
万方数据