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基于FPGA的国密算法SM4和ZUC可重构设计

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提出了一种SM4和ZUC-256密码的硬件实现方案.首先对两个密码算法进行硬件语言描述,然后构建了两个可重构单元——可重构寄存器和可重构S-box单元,从而在实现两个密码算法的基础上,有效降低了资源消耗,提高了资源利用率.在现场可编程逻辑门阵列(field programmable gate array,FPGA)上进行硬件验证.结果表明,本密码可重构方案中的硬件开销有明显的降低.
Reconfigurable design of state secret algorithm SM4 and ZUC based on FPGA
This paper proposes a hardware implementation scheme of SM4 and ZUC-256 ciphers.This scheme first provided hardware language description for the two ciphers,and then two reconfigurable units—reconfigurable register and reconfigurable S-box unit were constructed.Accordingly,based on the realization of two password algorithms,resource consumption was effectively reduced and resource utilization was improved.Hardware veri-fication was carried out using a field programmable gate array(FPGA).The results showed that the hardware overhead in the password reconfiguration scheme was significantly re-duced.

SM4 cipherZUC-256 cipherreconfigurableregisterS-box unit

李燕然、严利民

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上海大学微电子研究与开发中心,上海 200444

SM4密码 ZUC-256密码 可重构 寄存器 S-box单元

国家自然科学基金资助项目

52107239

2024

上海大学学报(自然科学版)
上海大学

上海大学学报(自然科学版)

CSTPCD北大核心
影响因子:0.579
ISSN:1007-2861
年,卷(期):2024.30(3)
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