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高速时钟信号的测试点选择与分析

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为了实现对高速时钟信号质量的精确判别,在分析传输线阻抗匹配原理基础上,深入分析传输线反射对时钟信号质量以及传输时延的影响.以PCIE的一对参考时钟信号为例,进行时钟信号传输链路的建模仿真,通过对晶振源端pin脚以及终端匹配电阻pin脚信号仿真测试波形的对比,发现终端匹配电阻pin处时钟信号单调性更好,因此提出高速时钟信号最佳选择终端匹配电阻pin脚的测试点,以减小传输线发射对信号的影响,便于后续产品的调试生产.
Test Point Selection and Analysis of High Speed Clock Signal
In order to achieve accurate discrimination of high-speed clock signal quality,this paper analyzes the influence of transmission line reflection on clock signal quality and transmission delay based on the analysis of transmission line impedance matching principle.Taking a pair of PCIE reference clock signals as an example,mod-eling and simulation of clock signal transmission link are carried out.Compared the signal at the pin of crystal os-cillator with the signal at the pin of terminal resistance,it is found that the monotone of the clock signal at the ter-minal matching resistance pin is better.Therefore,it is proposed that the test point of the terminal matching resist-ance pin is the best choice for high-speed clock signal,so as to reduce the impact of transmission line reflection and facilitate the debugging and production of products.

clock signal testingtransmission line reflectiontest point

张子春、刘婷婷、杨开泰

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中国航空工业集团公司西安航空计算技术研究所,陕西 西安 710065

时钟信号测试 传输线反射 测试点

2024

山西电子技术
山西省电子工业科学研究院 山西省电子学会

山西电子技术

影响因子:0.197
ISSN:1674-4578
年,卷(期):2024.(4)