Design and application of a NAND flash reliability verification experimental platform
[Objective]Flash memory is a type of storage medium that does not lose data when power is dropped,which has the advantages of high integration and low power consumption.Because of its high read/write speed and low price,the NAND flash is suitable for storing large amounts of data and is applied in high-speed storage domains,compared with other flash memories.However,the NAND flash memory encounters data wear and erasure error problems during data reading and writing,which considerably shortens its lifetime.Furthermore,the tracking and analysis of the aforementioned problems is infeasible,and there are no experimental devices designed for undergraduate students to intuitively experience the change in NAND flash performance over time.[Methods]Thus,a NAND flash memory performance test platform,which analyzes the reliability and performance characteristics,is proposed in this study.Micron's MLC 8 GB NAND flash memory chip is the experimental target,and the Nexys 3 FPGA development board is used to establish the memory test platform.The high density of I/O pins,which connect the FPGA board and the target flash memory chip,will complicate the connection process and affect the stability of high-speed data transmission.We designed a PCB subboard and used a VHDCI connector to ensure the stability of the FPGA board and data transmission of the NAND flash memory chip.In this study,we propose the supporting software for the platform,which can describe the topic design,control the experiment process,and analyze the experimental data.After analyzing the external pins,internal logic,and executing operation commands of the flash memory controller,serial communication,and top design,we modified the MLC chip mode to control the flash memory chip on the FPGA.This study also describes in detail the transmission of the commands to be executed on the FPGA and analyzes the received data to extract the features of the target MLC chip,such as the read/write latency,data loss rate,and erase delay.[Results]The experimental results show that:① As the number of P/E increases,the erase delay increases in steps and stabilizes after reaching a certain point,which reaches the lifetime at the 50,000th P/E,leading to stability failures.② The write latency decreases with the P/E number and decreases sharply at the beginning of the P/E operation;then,the decline rate gradually slows down.Moreover,the write delay changes more regularly and predictably than the erase delay,which is more likely to be predicted by constructors.③ The read delay is slightly affected by the increase in the P/E number and fluctuates within a small range,which indicates that the read delay is nearly unaffected by the increase in P/E.Using the designed NAND flash memory performance verification experimental platform,the reliability and performance characteristics of the target MLC chip can be observed and analyzed by undergraduate students.A series of experiments are set up during the implementation process,testing,and result analysis of the platform.[Conclusions]The proposed experiments cover courses and thematic experiments,open innovation projects,and graduation design.This platform is beneficial for cultivating the combination of theory with practice,independent thinking,and engineering problem-solving abilities of undergraduate students.
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