Design and simulation of SM3 algorithm hardware architecture based on Verilog hardware description language
[Objective]With the rapid development of the Internet of Things and network communication technology,cryptography has advanced significantly.Current hash function software can process multiple messages in parallel,making hash functions widely applicable for file tamper-proofing and software installation verification on mobile phones.However,existing hash function software often suffers from low speed and throughput,which hinders the processing of large-scale data in Internet of Things applications.Algorithm hardware can efficiently process large-scale data through algorithm adaptation and path optimization.Consequently,this experiment designs a hardware circuit for the SM3 cryptographic hash algorithm using Verilog hardware description language(HDL)to enhance the speed and throughput of the algorithm,thereby addressing the demand for high-speed hashing algorithms in Internet of Things applications.[Methods]This paper examines the speed and throughput of hash algorithm hardware using various optimization technologies and loop expansion methods.By comparing different techniques,the experiment presents an optimized SM3 hash algorithm.The Verilog HDL code implements the hardware circuit for the SM3 cryptographic hash algorithm,which is simulated using ModelSim by Mentor Graphics Corporation.According to the simulation results from the static sequence,the experiment identifies the critical path of the hardware.Leveraging this static sequence analysis,the study employs loop expansion technology and the conditional-select adder(CSA)to enhance processing speed and shorten the critical path.Furthermore,the FPGA is used to implement the hardware system experimentally and conduct a sequence test to evaluate throughput.According to the experimental results,the hardware incorporates the two-in-one structure loop expansion technology,which reduces two-step calculations to one step.As a result,the number of iterations for compression decreases from 64 to 32.This structure significantly improves calculation efficiency and reduces processing time.Additionally,this experiment proposes a CSA tree topology in the critical path to minimize logic delay without compromising accuracy.[Results]The experimental results for the hardware circuit of the SM3 cryptographic hash algorithm indicated that:1)The initial and optimized delays were 6.006 ns and 5.525 ns,respectively,according to the simulation results from ModelSim.This represents a reduction in delay of 0.481 ns for the hardware circuit.2)The proposed CSA tree topology in the optimized hardware system reduced logic delay by 8.01％experimentally,further enhancing overall calculation speed and efficiency.3)The two-in-one loop expansion technology implemented in the optimized hardware system increased throughput from 822.4 Mb/s to 1 069.5 Mb/s,achieving an improvement rate of 30％.[Conclusions]By incorporating the two-in-one structure loop expansion technology and the CSA tree topology,the hardware circuit for the SM3 cryptographic hash algorithm in this experiment shortens the critical path and reduces logic delay.As a result,calculation speed and efficiency are greatly enhanced.The presented hardware circuit achieves high speed and throughput,enabling the processing of large-scale data without time expansion.Overall,this study significantly contributes to the processing of large-scale data in the Internet of Things and network communication technology.
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维普
