一种适用于小尺寸工艺的SRAM单元设计
A New SRAM Cell Design for Nano-Scale Technology
王媛媛 1王子欧 1张立军1
作者信息
- 1. 苏州大学电子信息学院,江苏苏州215006
- 折叠
摘要
最近研究表明，静态存储器（SRAM）功耗是整个芯片功耗的重要组成部分，功耗问题在SRAM单元设计中成为一个日益重要的问题。提出了一种新的纳米级的高稳定性和低功耗应用技术，采用该技术的SRAM单元采用分开的读写机制。65nmCMOS工艺的仿真结果表明，此新型的SRAM单元结构在保证正确的读写操作下，在写0操作时功耗比传统的SRAM单元降低22．45％。同时，此新型SRAM在空闲模式下利用漏电流和正反馈存值，极大地提高了SRAM单元的稳定性，改善了纳米尺度下SRAM单元的功耗问题。
Abstract
Power consumption is becoming a pressing issue in SRAM cell design. Recent research shows that SRAM power contributes a key part of the whole chip power consumption. In this paper, we present a new 6T-SRAM cell structure for nano-scale technology with stability of low power application by using separate write and read operation. Simulation results with standard 65nm CMOS technology show the correct operation, the speed is closed to the traditional 6T cell, power consumption reduces about 22.45% during write 0. In particular, this structure maintains its data with leakage current and positive feedback in idle mode which can greatly improve the power consumption of the nano-scale SRAM.
关键词
稳定性/低功耗/漏电流/SRAM设计Key words
stability/low power/leakage current/SRAM design引用本文复制引用
出版年
2012
NETL
NSTL
维普
万方数据