一种应用于流水线ADC中的低压高速采样/保持电路
A Low-Voltage High-Speed Sample-and-Hold Circuitfor Pipelined ADCs
陈阳 1骆敏 1鲁征浩1
作者信息
- 1. 苏州大学电子信息学院,江苏苏州215006
- 折叠
摘要
介绍了一种用于流水线模数转换器前端的低电压、低功耗、高速采样/保持电路。该电路基于电容翻转型结构,采用全差分折叠共源共栅两级运放,能实现高增益、大单位增益带宽和大摆幅。在SMIC 0.13μm工艺、1.2V电压下仿真,其性能满足10bit精度、120MHz采样频率的ADC的要求,整个电路功耗约15mW。
Abstract
We present the design of a high-speed,low voltage and low power sample-and-hold circuit(S/H)for pipelined analog digital converter(ADCs) at the front end.This circuit is based on capacitor flip-around architecture with fully differential folded cascade two-stage operational transconductance amplifier(OTA),which has the advantage of the high DC gain,large unity gain bandwidth and large swing.The entire S/H circuit is designed in SMIC 1.2V 0.13μm CMOS technology and the 10bit resolution at 120MHz sampling rate is achieved.The total power dissipation is about 15mW.
关键词
采样/保持电路/两级运放/低电压Key words
sample/hold circuit/two-stage OTA/low voltage引用本文复制引用
出版年
2012
NETL
NSTL
维普
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