A Low-Voltage High-Speed Sample-and-Hold Circuitfor Pipelined ADCs
We present the design of a high-speed,low voltage and low power sample-and-hold circuit(S/H)for pipelined analog digital converter(ADCs) at the front end.This circuit is based on capacitor flip-around architecture with fully differential folded cascade two-stage operational transconductance amplifier(OTA),which has the advantage of the high DC gain,large unity gain bandwidth and large swing.The entire S/H circuit is designed in SMIC 1.2V 0.13μm CMOS technology and the 10bit resolution at 120MHz sampling rate is achieved.The total power dissipation is about 15mW.
NETL
NSTL
万方数据
维普
