首页|Doped low-density parity-check codes

Doped low-density parity-check codes

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In this paper,we propose a doping approach to lower the error floor of Low-Density Parity-Check(LDPC)codes.The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code.Accordingly,an algorithm for selecting the information bits of the short code is proposed,and a specific two-stage decoding algorithm is presented.Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10-6.Furthermore,the proposed design can lower the error floor of original LDPC codes.

LDPC codesDoped LDPC codesTanner graphQuadratic residue codesTrapping sets

Yong Li、Rui Liu、Xianlong Jiao、Youqiang Hu、Zhen Luo、Francis C.M.Lau

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College of Computer Science,Chongqing University,Chongqing,400044,China

School of Automation,Chongqing University,Chongqing,400044,China

College of Electronic and Information Engineering,Southwest University,Chongqing,400715,China

Future Wireless Networks and IoT Focusing Area,Department of Electronic and Information Engineering,Hong Kong Polytechnic University,Hong Kong,China

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NSFNSF中央高校基本科研业务费专项Project of Chongqing Natural Science FoundationScience and Technology Research Project of Chongqing Education CommissionVenture and Innovation Support Program for Chongqing Overseas Returnees

6177108162072064cstc2019jcyjmsxmXO110CSTB2022NSCQ-MSX0990KJQN202000612cx2020070

2024

10.1016/j.dcan.2022.11.013

数字通信与网络(英文)

数字通信与网络(英文)

ISSN：
年,卷(期)：2024.10(1)
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