DDR SPD is a key device for obtaining memory parameters and conducting memory training.At present,DDR SPD has evolved to the 5th generation,upgrading from the traditional I2C interface to the I3C interface.This article introduces the design composition and logical implementation principle of the I3C module that currently needs to be integrated into processors.At the same time,simulation verification was conducted on the FPGA platform.By connecting the actual DDR5 RDIMM,access to SPD5118 devices on the DIMM and other devices mounted on the LSCL/LSDA bus was completed,and the basic data path function of the module was verified.The applicability of bus IO PAD was explored.
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