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Wi-Fi接收机的高效频率偏移估计电路设计

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频率偏移估计能够保证正交频分复用系统中符号间的正交性,是 Wi-Fi 接收机进行信号处理的重要步骤.针对频率偏移估计电路设计面临的计算精度与资源消耗的权衡难题,设计了一种高效率的频率偏移估计电路.首先,对频率偏移估计数据处理流程进行总体仿真,探究不同数据位宽对估计结果的均方根误差的影响.并对各级中间变量的动态范围进行细粒度划分,确定各级中间变量的合适数据位宽和截断方式,在保证数据精度的同时节约硬件资源.其次,采用一种基于查找表的复数相角计算单元,通过查表和近似计算提高电路性能.通过此方法可以降低逻辑资源消耗超过 96.9%,减少 95%的执行周期数.最后,通过时分复用设计使粗、精频率偏移估计共享硬件资源,并通过优化流水线结构进一步减少电路的资源消耗、提高数据处理速度.实验结果显示,在信噪比为15 dB 时,与粗频率偏移估计电路相比,设计的电路使 Wi-Fi 接收机误码率降低了约 17.94%;与分别进行粗、精频率偏移估计的电路相比,查找表消耗数量降低了 71.22%,功耗降低了 24.73%,处理所需周期数降低了 22.90%.所设计的频率偏移估计电路最终实现了资源消耗和计算精度的优化.
Efficient Frequency Offset Estimation Circuit Design for Wi-Fi Receivers
Frequency offset estimation ensures orthogonality between symbols in an orthogonal frequency division multi-plexing system,and it is an important step for signal processing in Wi-Fi receivers.Addressing the trade-off be-tween computational accuracy and resource consumption while designing frequency offset estimation circuits,one such high-efficiency circuit was designed in this study.First,the simulation of the data processing flow of frequency offset estimation was performed to explore the effect of different data-bit widths on the root mean square error of the estimation results.Further,the dynamic range of intermediate variables at each level was divided into fine grains,and appropriate data-bit widths and truncation methods of intermediate variables at each level were determined to save hardware resources while ensuring data accuracy.Second,a complex phase angle calculation unit was used to im-prove the circuit performance using look-up tables and approximation calculations.This method can reduce logic re-source consumption by more than 96.9%and the number of execution cycles by 95%.Finally,coarse and fine fre-quency offset estimation shared hardware resources using the time division multiplexing design.The resource con-sumption of the circuit was further reduced,and data processing speed was increased by optimizing the pipeline structure.The experimental results showed that at a signal-to-noise ratio of 15 dB,the designed circuit reduced the bit error ratio of the Wi-Fi receiver by about 17.94%compared with that of the coarse frequency offset estimation circuit.In addition,the number of look-up tables consumed was reduced by 71.22%,power consumption was reduced by 24.73%,and the number of cycles required for processing was reduced by 22.90%compared with circuits that per-formed coarse and fine frequency offset estimation,respectively.The designed frequency offset estimation circuit ultimately optimized resource consumption and computational accuracy.

Wi-Fifield programmable gate arrayfrequency offset estimation

刘强、伍问岳

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天津大学微电子学院,天津 300072

Wi-Fi 现场可编程门阵列 频率偏移估计

2025

天津大学学报
天津大学

天津大学学报

北大核心
影响因子:0.793
ISSN:0493-2137
年,卷(期):2025.58(2)