基于DWC PCIE Core的数据传输系统设计
Design of Data Transmission System Based on DWC PCIE Core
刘肖婷1
作者信息
- 1. 北京全路通信信号研究设计院集团有限公司,北京 100070;北京市高速铁路运行控制系统工程技术研究中心,北京 100070
- 折叠
摘要
在铁路信号系统中,为有效减少铁路信号系统设备CPU资源占用率,设计一种基于DWC PCIE Core的数据发送与接收系统.该系统采用内嵌ARM Cortex-A9双核的FPGA开发板套件,利用FPGA的灵活性和可扩展性,采用可配置的PCIE硬核IP模块以及以太网硬核IP模块.该系统主要介绍Host PC与FPGA之间基于PCIE 2.0的DMA数据传输以及FPGA之间基于GMAC的以太网数据传输,通过PCIe总线、以太网基于DMA模块实现数据高速可靠传输.
Abstract
In the railway signaling system,a data sending and receiving system based on DWC PCIE Core is designed to reduce the CPU resource occupancy of railway signaling system.The system adopts FPGA development board suite embedded with ARM Cortex-A9 dual core,which takes the advantage of the flexibility and scalability of FPGA,and uses configurable PCIE hard core IP module and configurable Ethernet hard core IP module.This paper mainly introduces the realization of high-speed and reliable data transmission through PCIE bus and Ethernet based on DMA modules between Host PC and FPGA and between FPGA boards.
关键词
DWC/PCIE/Core/FPGA/数据传输/DMAKey words
DWC PCIE Core/FPGA/data transmission/DMA引用本文复制引用
基金项目
国家重点研究计划(2022YFB4300600)
出版年
2024
国家科技期刊平台
NSTL
维普
万方数据