Design of Multi-Chip Synchronization Automatic Correction Based on JESD204B Deterministic Delay
Aiming at the problem of deterministic delay in stability,reliability and repeatability of high-speed analog-to-digital converter JESD204B interface multi-chip synchronization system,a solution scheme is proposed.Based on the synchronization principle of subclass 1,the scheme can automatically correct the repeatable deterministic delay by automatically correcting the setup and hold time of reference clock relative to the device clock and using the deterministic delay principle.The technology of adjustable SYSREF delay and automatic correction of internal detection mechanism of analog-to-digital converter is adopted to determine the optimal delay time and realize fixed phase sampling of multi-chip analog-to-digital converter.At the receiving end of the programmable logic chip,the relative position of data arrival with the local multi-frame clock is automatically corrected,thus establishing a stable and repeatable deterministic delay.The design is helpful for multi-chip synchronization system to better cope with harsh environment and self-sensitive delay changes.
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