Design and Implementation of VLSI for Lossless Image Compression Based on 2D Wavelet Transform
A hardware architecture for 2D discrete wavelet transform(DWT)based on the 5/3 lifting scheme is proposed.The architecture employs a parallel input-output structure for the entire DWT process,using internal RAM to temporarily store intermediate variables during computation.A three-stage pipeline structure is applied to the design of both row and column filters,and a transposition unit with simple logic and small memory is designed.The external RAM storage space is reduced,and 5 RAMs are used to store wavelet coefficients.Through experiments on a XILINX KC705 FPGA,a lossless compression system is implemented,and four images are compressed with compression ratios ranging from 1.3 to 2.The design saves hardware resources,reduces critical path delay,and the DWT module can operate at a frequency of up to 219 MHz,demonstrating certain technical advantages in practical applications.
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维普
