Design of a CRC Circuit Applicable to Multiple Verification Standards
The design of two different structures of Cyclic Redundancy Check(CRC)code generation circuits based on Linear Feedback Shift Registers(LFSR)is presented.The polynomials and orders of these circuits can be adjusted through configuration registers,making them applicable to communication systems with various international standard CRC generation polynomials.Circuit improvements and design concepts are elaborated upon,an RTL-level description of the circuits using Verilog language is provided,and the syntax and synthesizability of the code are verified using Synopsys VCS tool,and the functional simulations of the circuits are conducted.The simulation results validate the correctness and effectiveness of the design,providing theoretical guidance and practical experience for integrating circuits applicable to various CRC verification standards in System-on-Chip(SOC)designs.
万方数据
维普
